1. Technical Field
The present disclosure relates to a delay locked loop circuit and a method for controlling the same and, more particularly, to a delay locked loop circuit and a method for controlling the same that are capable of compensating for delay according to voltage variations.
2. Discussion of Related Art
With the rapid development of semiconductor technology, digital systems such as personal computers, personal digital assistants (PDAs), and portable communication devices have been advanced in capabilities over the past several years. The operational speed and data transmission rate of peripheral devices, such as memories, communication devices, or graphic devices have also been improved. Because the operational speed of the peripheral devices cannot keep pace with operation speed of microprocessors, however, there is always a speed difference between new microprocessors and their corresponding peripheral devices. Accordingly, high-speed peripheral devices have been required for a high-performance digital system.
For example, in an input/output system in which data transmission is performed in synchronization with a clock signal, as in data transmission between a memory device and a memory controller, temporal synchronization between the clock signal and the data is very important as the load on a bus increases and the transmission frequency becomes higher. To achieve the necessary temporal synchronization, a phase locked loop (PLL) circuit and a delay locked loop (DLL) circuit may be used.
In general, the delay locked loop (DLL) is used to synchronize an internal clock of a synchronous memory to an external clock. That is, the delay locked loop (DLL) is used to synchronize the internal clock to the external clock when a delay time is generated upon using the external clock inside the memory.
FIG. 1 is a block diagram illustrating a conventional delay locked loop circuit.
Referring to FIG. 1, the conventional delay locked loop circuit comprises a delay chain 10, a phase interpolator (PI) 20, a phase selection and control unit 30, a phase detector (PD) 40, and a replica path (RP) 50.
The delay chain 10 comprises a plurality of delay cells (D). The delay chain 10 delays an external clock signal ECLK, which is a reference clock input from an external device, by a predetermined time and outputs a delayed clock signal. A delay amount of the delay chain 10 is controlled by the phase selection and control unit 30 according to a phase difference between the external clock signal ECLK and a clock signal fed back via the replica path 50.
The phase interpolator 20 properly controls two clock signals with different phases to generate a clock signal with a phase between the two clock signal phases. An interpolation circuit is used in a variety of application circuits because of its capability of outputting a precise desired phase. The phase interpolator 20 interpolates the clock signal output from the delay chain 10 to generate a clock signal with a suitable phase.
The replica path 50 is a circuit having the same delay condition as an actual clock path, such as a ‘tSAC path’ 60, for delivering the clock signal from the phase interpolator 20 to a final data output terminal of the semiconductor memory device (not shown). The replica path 50 is also called a replica circuit. The clock signal replicated and fed back by the replica path 50 has the same phase as the clock signal delivered to the final data output terminal of the semiconductor memory device (not shown).
The phase detector 40 compares the phase of the external clock signal ECLK with the phase of the clock signal fed back from the replica path 50 and outputs the comparison result to the phase selection and control unit 30.
The phase selection and control unit 30 determines whether to increase or decrease the delay amount of the delay chain 10, based on the comparison result from the phase detector 40, and adjusts the delay amount of the delay chain 10 according to the determination result.
In this manner, the delay locked loop circuit locks the clock signal on the final data input/output terminal of the memory device to be synchronized to the external clock signal ECLK. That is, the delay time generated in the course of delaying the clock signal using the delay locked loop circuit and delivering it to the final data input/output terminal is replicated and fed back by the replica path 50. Thus, the delayed clock signal is locked by controlling the delay amount of the delay chain 10 according to the phase difference detected between the external clock signal ECLK and the fed back clock signal, so that the clock signal used in the final data input/output terminal is synchronized to the external clock signal ECLK.
In this conventional delay locked loop circuit, delay amounts of the actual clock path, that is, the tSAC path 60, and the replica path 50 vary with variations of an operation voltage. In this case, a logic failure may occur due to insufficient delay cells of the delay chain 10.
This phenomenon may occur when an operation voltage is unstable or when a test is performed with a changing operation voltage. In general, as the operation voltage changes from a low level to a high level, the delay in the replica path 30 decreases. This is compensated by increasing the number of delay cells in the delay chain 10 of the delay locked loop circuit. When the operation voltage changes from a high level to a low level, the delay of the replica path 30 increases. This is compensated by decreasing the number of the delay cells. When the change in the operation voltage is too great to compensate for, through an increase or decrease in the number of delay cells in the delay chain 10, the logic failure occurs.
To prevent or minimize such a logic failure, sufficient delay cells of the delay chain 10 are required. That is, when the operation voltage changes from a low level to a high level, the number of selectable delay cells must be sufficient. When the operation voltage changes from the high level to the low level, a number of selectable delay cells must be required to reduce a delay time.
Increasing the number of the delay cells, however, increases layout area and power consumption. Accordingly, there is a need for a technique of preventing and minimizing logic failure, while minimizing the layout area and power consumption.